EDA News Monday December 15, 2003 From: EDACafe ÿÿ Previous Issues _____ Cadence _____ About This Issue True Circuits' Stephen Maneatis More on the business and technology of IP _____ December 8 - 12, 2003 By Peggy Aycinena Read business product alliance news and analysis of weekly happenings _____ Stephen Maneatis is the CEO of True Circuits, Inc. The following commentary on the business and technology of analog IP were made during a recent lengthy phone call and provide an interesting point/counterpoint to the comments from Adam Kablanian in the December 1st issue . Please read for the larger lessons, not for the specifics or the messaging about the company. "True Circuits is a provider of analog and mixed-signal IP for the semiconductor, systems and electronics industries. Our focus now is on timing IP, which we license through library partners and directly to end customers. We're seeing a strong pickup in a number of market segments right now - both with IDMs and with smaller AISC and FPGA firms - which is exciting for us as it means an increase in licensing of our IP." "These days, analog and mixed-signal IP are viewed as one and the same. A customer is either buying digital or analog/mixed-signal IP. These involve two different areas of design expertise with different competencies. Of course, it's analog/mixed-signal IP that's gaining in importance as more and more chips are developed for communication applications, so that is good for us." "There are a lot of physical issues at 130 nanometers or 90 nanometers that an analog engineer has challenges with - shrinking a digital design is doable as you move to smaller process nodes, but shrinking an analog circuit is just not that simple. And right now, we're seeing a shortage of experienced analog engineers. For instance, we hired an employee within this past year who was a digital engineer - a very smart guy - and with some training and mentorship, he was able to pick up on the analog issues and successfully perform mixed-signal design work. But more typically, you've got engineers who are trained, or are passionate, either in digital or in analog - but not both." "I see two issues at work in the IP industry today. First analog/mixed-signal design is getting harder and harder, while at the same time, large companies have been dispersing these niche design teams as part of their downsizing efforts and small ASIC and FPGA companies are now entering the market. Over the last several years, this has made outsourcing IP development the only way many of these companies can complete their complex chips. If you look back 5 to 10 years, you would see that large companies had large engineering staffs to work on timing and interference designs and related issues. But as we've seen the strong trend toward outsourcing over the last couple of years, many companies no longer have that kind of expertise in-house. Design reuse and third-party IP have now become a necessary and economical way of getting products to market without having [to bear the burden of] in-house analog/mixed-signal design teams." "Second, there are concerns about the quality and reusability of IP. Is it practical for a company to license and use IP from a third party that is basically a black box and be confident that the IP will work after it's integrated into their design? Related to that, can a customer truly reuse the third party IP and thus amortize its cost over the lifetime of the product? This second issue is where companies, both big and small, have an aversion to licensing IP." "But the biggest concern for customers is whether the IP they've licensed will work, and on first silicon. If I can tell them that this or that piece of IP has been proven in silicon, they're more confident about using it. When you're a vendor that offers a large portfolio of IP across any vendor or process, not every design in the portfolio will have been proven in silicon. Customers will naturally have concerns about that, particularly as they know that integrating IP into small geometries and dealing with ever changing standards is tough. So our focus is on providing timing IP that is very robust and has been optimized for performance throughout wide operating ranges. We want the customer to be able to drop our IP into their chip and know that it's broad enough in its design and flexible enough by its pin-programmability that changes in the larger design of the chip can be accommodated by the original piece of IP rather than requiring compromises." "Of course, we always emphasize to our customers that we're really good at what we do - that our IP is robust, standardized, reusable, and that we provide the support and training required to use it optimally in their chip application. If our first engagement with a customer goes well, they're more at ease with considering a second engagement with us. We feel what really distinguishes between IP companies is whether the IP is standardized enough to use and reuse - and that's why we've made a great deal of effort to develop the core circuit technologies and the design flows that allow us to produce each piece of IP in a standardized way. Our IP is available across a range of functionalities, process generations, and fabrication vendors. We do considerable amount of R&D and are constantly improving our circuit technologies. Using our proprietary CAD environment and design flows, we can easily port new technologies to new or old process generations and to any fabrication vendor. We've got a broad portfolio of timing IP - DLLs and PLLs - and our customers can pick any item from our IP catalog, license it, and know that we'll provide a hard macro ready to integrate into whatever chip or circuit they're designing. It's a seamless process." "Again - this is something that distinguishes the different IP companies. Some third-party vendors just want to throw their IP over the fence to their customers and let the customers struggle with the integration. That's not our business model. We spend a great deal of time optimizing our designs and user documentation before sending an IP hard macro to a customer, and although we are always ready to provide support, our IP is such that in more than 50 percent of the cases, a few phone calls at the outset of the integration process is all that's needed for the customer to proceed. The second time around rarely even requires a phone call. Our goal as a company is to get to the point that we need to offer zero support - that we've understood a customer's requirements and provided the right IP that they can easily integrate and reuse. If a customer is satisfied the first time and they know we've got good IP and a good support model - we'll win that customer for life." "Meanwhile, there's an evolution underway in the industry with regards to licensing models - models that build up-front relationships between the IP provider and their customers. Right now, we have a license fee model that does not involve royalties. Our customers pay a license fee at various milestones - at delivery of the IP, at tape-out to fab, and when the IP is proven in silicon. If the customer wants to use that piece of IP multiple times in their chip design, they can do so for no additional fee. However, if they want to use it later in a different chip design, they only pay a reuse license fee - typically 50 percent of the original first-time license fee. There is no per-part royalty, so all IP cost is known and paid upfront." "There are potential issues with IP piracy. We track reuse by building relationships with the companies we work with. Of course there's an honor system associated with all of this. And now that we're working with more and more customers, we are happy that the VSIA tagging system - complete with IP reference number - is in place so the major fabs can look at the appropriate layer in a chip and verify that a particular piece of IP is being used by that customer." "Our current strategy is primarily based on the honor system. It requires the players [in the design and manufacturing chain] to report out on their use of our IP. Our biggest concerns are, therefore, that our IP can be reused by a current customer without a fee being paid, or worse, that it might be reverse engineered or propagated - ending up systematically incorporated into other companies' technology. At this time, we have quite a number of patents either issued or pending on our IP. We always make sure the patent process is in place before we publish in leading technical journals - and we make sure that the licensing agreements are clear and up to date." "Customers have intellectual property protection issues of their own. When we first engage with a potential customer, we always sign mutual NDA agreements to ensure confidentiality with respect to their pending chip project and our IP. There are actually a number of legal remedies that you can pursue to protect a situation. After all, potential customers have to be able to look at our IP and understand if they can integrate it into their code, so there's an inevitable degree of visibility there, although we never provide customers with the actual schematics. We're always aware, however, that when someone has got your GDSII and the things that go with it - they might, unfortunately, decide to pursue a direction that's parallel with what we've done." "Right now, we're building partnerships with large companies like Texas Instruments, who licenses a family of our PLLs and DLLs for external and internal ASIC designs. We're also building partnerships with design services firms who are distributing our IP and doing the integration work. Lastly, we're pursuing closer relationships with our fabrication partners so we can improve our circuit technologies to be even more robust and tolerant in silicon. Big company or small - they can all license our timing IP." "Most importantly, I think that IP - particularly third-party IP - has gotten a bad rap in the past, so the more press that IP gets the more that people will believe that designs can be reusable, that IP vendors are truly good at what they do. If IP isn't written or talked about, the industry won't grow. IP provided by experts in their field of design is not evolutionary - it can be revolutionary. And it's practical from both a technical and a business point of view to let the experts do the real complex design work. The final transition will be when there is total acceptance that our kind of IP - complex analog and mixed-signal IP - can be licensed and a single piece of IP can work in a range of chip designs. We're on the up-slope of adoption of this kind of technology, but we are moving forward." Industry News - Tools and IP Actel Corp. announced it has enhanced its Libero Integrated Design Environment (IDE) to include Magma Design Automation' PALACE (Physical And Logical Automatic Compilation Engine) physical synthesis tool. Actel's OEM agreement with Magma arranges for PALACE - which Magma says provides an average of 20 percent higher performance for ProASIC Plus FPGAs - to be available from Actel as a standalone tool or bundled with Actel's Libero IDE. Actel also announced that the Silver and Gold Editions of the Libero v5.1 IDE now provide device support for up to 300,000 gates. Saloni Howard-Sarin, Director of Tools Marketing at Actel, is quoted in the Press Release: "Now integrated as part of Actel's development tools portfolio, the PALACE physical synthesis tool from Magma offers a simple interface that requires little user intervention." Also from Actel - The company announced the availability of a high-density ceramic column grid array (CCGA) packaging "solution" for the company's radiation-tolerant and military-qualified FPGA devices. Actel says the new packaging technology packs 2.5x the I/O density in 90 percent of the footprint available in Actel's existing packages. The company also says that the CCGA624 package "offers an unparalleled combination of density and reliability with minimal board real estate." The hermetically sealed CCGA package has been developed for "mission-critical" systems - satellite bus and payload subsystems of commercial and military spacecraft, where high levels of reliability and tolerance to thermal stresses in a small footprint are needed. Per the Press Release: "An attractive alternative to the ball-grid array, the CCGA package utilizes 624 high-temperature solder columns to create a higher standoff and provide greater tolerance to the stresses caused by different rates of thermal expansion between the PCB and the package. As a result, the thermal fatigue life of the package solder joints is significantly increased. Additionally, the solder columns can be placed as much as 50 percent off the center of the PCB's landing pad and provide sufficient flexibility to realign properly with the pad during solder flow operations." Ken O'Neill, Director of Military and Aerospace Product Marketing at Actel, is quoted: "Continuing our heritage as the FPGA leader in the space and military markets, Actel is committed to providing innovative FPGAs and intellectual property cores to the community. In keeping with our legacy, the high-density CCGA packaging solution extends the benefits of our radiation-tolerant and military-qualified FPGA product portfolio to better meet the requirements of applications where tight physical constraints demand the highest levels of integration." Agilent Technologies Inc. introduced a new simulation model for high-frequency Gallium Arsenide (GaAs) and Indium Phosphide (InP) heterojunction bipolar transistors (HBTs). The HBT model for Agilent Advanced Design System (ADS) software is designed to provide "greater accuracy and improved convergence over existing HBT models. This helps reduce design turns and shorten the design cycle of high-frequency ICs for applications such as power amplifiers for wireless handsets and wireless local area networks." Per the Press Release: "Today, many high-frequency circuits are designed in GaAs or InP HBT processes. Many existing GaAs HBT models use models originally created for silicon bipolar junction transistors (Si BJTs). Using existing Si BJT models to simulate GaAs or InP HBTs for high-frequency IC design contributes to inaccurate and incomplete results for large-signal nonlinear circuit simulations. Agilent's HBT model is designed specifically for GaAs and InP processes used in high-frequency design, and supports both single and double heterojunctions. The new model is based on research originally performed by a working group led by the University of California San Diego (UCSD) for a GaAs physics-based model known as the DARPA/UCSD HBT model." Ansoft Corp. released ePhysics, software that the company says expands the capabilities of the Ansoft's HFSS and Maxwell 3D tools. The company also says that with ePhysics, engineers can now incorporate three-dimensional steady-state thermal, transient thermal and linear stress analysis into their existing electromagnetic-based design flows. Zoltan Cendes, Chairman and CTO at Ansoft, is quoted in the Press Release: "The combination of increasing frequencies and dissipated power, together with reduced size and weight, has made temperature and stress a great concern to electrical/electromagnetic engineers designing present-day electrical devices. Often a product's lifetime and/or performance metric is greatly reduced by excessive temperatures and stresses that result from electromagnetic heating and forces. In other cases, electromagnetic heating and stresses can be harnessed to achieve desired design goals. In either case, ePhysics extends our core experience in electromagnetic analysis to enable electrical/electromagnetic engineers to optimize their designs for maximum performance and cost efficiency." BindKey Technologies announced that Tower Semiconductor Ltd. has selected BindKey's RapiDesignClean rules-driven layout "solution" to be part of Tower's standard IC design methodology. BindKey describes RapiDesignClean as "the industry's first rules-driven layout solution for custom design of nanometer ICs." Tower says it selected RapiDesignClean to support increased demand for engineering resources that is a result of the growing number and complexity of the company's design rules. Sergio Kusevitzky, Vice President of IP and Design Services for Tower, is quoted in the Press Release: "On its own, RapiDesignClean has increased layout productivity by more than 20 percent. Our engineers can quickly acquire high proficiency in new processes because RapiDesignClean significantly reduces the need to memorize complex rule sets. This provides flexibility in moving engineers between projects, thus optimizing the company's resources. Moreover, we are able to complete designs in a single iteration as RapiDesignClean is applying the same design rules as our sign-off DRC tool." Cadence Design Systems, Inc. announced that it has "supported" Motorola in delivering a complex IC design with 62+ million transistors. Cadence says it provided engineering services and a complete back-end design flow at 130 nanometers, and that it helped Motorola "transition from a non-Cadence flow to a completely new methodology based on the Cadence Encounter digital IC design platform." The companies say that the new flow is targeted at TSMC's 130-nanometer technology, and that this particular situation allowed Motorola to progress from final netlist to tape-out in six weeks. The end product was the MRC6011, a "highly programmable reconfigurable compute fabric (RCF) device," which Motorola says combines "system-level flexibility and scalability with the cost-competitive and low-power consumption characteristics of an ASIC-based device." Also from Cadence - The company announced that Faraday Technology Corp. has developed a design implementation flow for its Metal Programmable Cell Array (MPCA) structured-ASIC technology, using Cadence's Encounter platform. The companies say that Cadence is "the first EDA vendor to enable Faraday to conduct actual chip implementation methodology with its structured ASIC paradigm. Faraday's structured ASIC implementation flow was based on Cadence's leading-edge continuous convergence methodology provided by the Cadence Encounter platform. The flow was successfully validated with an actual test chip tape-out in May 2003. The major benefit of the flow is that it helps Faraday engineers drive its customer design netlist from a structured ASIC floorplan specification to a physical design, with fast and guaranteed timing and signal integrity closure." From Cadence, as well - The company announced that TSMC has "validated" Cadence's Fire & Ice QXC for the TSMC's Nexsys process, and that Fire & Ice QXC is "an accurate full-chip extractor, tackling in-die process variations inherent in 90-nanometer design. With new-generation 3-D models, Fire & Ice QXC correctly accounts for all copper and optical effects, enabling designers to reduce timing margins and improve the performance and yield of their designs." Genda Hu, Vice President of Corporate Marketing for TSMC, is quoted in the Press Release: "Our collaboration with Cadence to verify Fire & Ice QXC allows mutual customers to take full advantage of TSMC's leading-edge process technologies." Denali Software announced that Unisys Corp. has licensed Denali's PCI Express verification tools for the development of the PCI Express interfaces in the Unisys ES7000 server chips. Unisys says its engineers are using Denali's PureSpec verification IP to model, simulate, and verify the interface between Unisys chips and other PCI Express compliant devices, and that by using PureSpec, Unisys engineers can expose potential interoperability bugs early on in the development cycle before the designs are implemented in silicon. Diep Nguyen, Hardware Engineer Manager at Unisys, is quoted in the Press Release: "Denali continues to be a key innovator with tools and technology for interface modeling and interoperability verification. Using Denali's PureSpec helps us verify that our designs are compliant with the PCI Express standard and interoperable with other PCI Express implementations." MIPS Technologies, Inc. announced that it is pleased that its "long-time partner" Toshiba has formed a strategic alliance with DENSO Corp. of Japan to develop car navigational devices for the automotive market. Per the Press Release: "Designers of automotive applications, such as navigation and infotainment products, are driven by the often conflicting demands of offering a rich car user experience while keeping costs down and getting to market quickly : The strategic partnership between Toshiba and Denso includes co-development and implementation of a multi-operating system (OS) platform that forms the basis for advanced SoC designs by enabling uITRON (the predominant embedded operating system for deeply embedded devices targeted for the Japanese market) and Windows Automotive in a single OS environment. This multi-OS environment will utilize the high-performance MIPS architecture to enable user applications, such as Internet and network connectivity and the display of audio and video content." Also from MIPS - The company announced that Genesis Microchip has taken a license for the MIPS32 4KEc core for use in its digital TV applications. Anders Frisk, Executive Vice President of Genesis, is quoted in the Press Release: "The 4KEc core from MIPS Technologies offers a high-performance applications processor that matches the overall system performance of our digital TV processors." ProDesign announced the CHIPit Silver Edition, which the company describes as "the newest member of the CHIPit family" - a rapid prototyping and IP verification platform that ProDesign says is designed for use in PCs and workstations. Per the Press Release: "The platform distinguishes itself through use of a VIRTEX-II FPGA from Xilinx, as well as with excellent memory resources and possibilities for expansion. The CHIPit Silver Edition communicates with its host, as do all products of the CHIPit range, via the ProDesign proprietary UMRBus Communication System. Using this technology, multiple independent communication channels between the host and a design can be set up, whilst the handling remains simple and intuitive. The CHIPit Silver Edition is particularly suited for co-emulation verification of IP cores, ASIC designs, or parts thereof - the optional HDL-Bridge package provides interfaces for the HDL simulators ModelSim and NCSIM. This package includes a tool for implementation of multiple IPs in hardware, which also gives the possibility of simultaneously spreading multiple IPs across multiple CHIPit Silver Edition platforms. As programming interfaces, the user has the choice between C/C++ and Tclk/Tk." Silicon Canvas Inc. announced its LakerT1 product, which the company says is a platform for Process Test Chip Development (PTD). Per the Press Release: "Laker T1 is the first commercial product of its kind. It can be used by pure foundry houses and IDM companies to calibrate and qualify IC process technologies. It can be also used by cutting-edge fabless houses, which have special devices of their own kind. Based on its relationships with the world's leading foundries such as TSMC, Silicon Canvas developed Laker T1 to enhance and streamline the conventional PTD flow. With Laker T1, cycles that usually took two years and three-to-six re-spins in the conventional flow can be shortened to eight months or less, and with only zero or one re-spin. Clients using T1 can realize a huge ROI from equipment depreciation alone, let alone other intangible benefits such as better yield, early time-to-market gains, and more flexible business models." "The PTD cycle is quickly becoming one of the leading barriers to market success for pure foundries houses and IDM companies. Escalating development costs combined with longer development lead times prohibit many fabs from placing complete and thoroughly scrutinized test structures and test lines into the test chips. The problem continues to feed on itself as the lack of critical correlation and test data makes their way though the PTD cycle." "For example, a 300mm wafer fab costs between $2B and $4B to build. Typical mask costs range from $750K for 130 nanometers to $3M for 65 nanometers. The conventional PTD models, most of which are created by trial-and-error, can take as long as 2 years to complete and require 3-to-6 correction spins - a methodology that obviously is no longer cost effective." "Designers who are using the services of a fab require a Process Test Chip Development approach that can reduce the re-spins and shorten the overall PTD cycle, while providing a systematic way to generate sufficient and meaningful data required to qualify a fab. With Laker T1's systematic reusable and scalable approach, foundries can easily create multitudes of test structures and test lines targeted at providing detailed coverage of the many different aspects of PTD. This will aid in obtaining faster convergence between the process' electrical performance and equipment resolution. In turn, the foundry can deliver a more comprehensive specification to the customer with overall increased confidence in design for manufacturability. The bottom line is a faster ramp-up time." Synopsys, Inc. announced Taurus Process Atomistic, which the company describes as "a new process simulation tool for sub-90-nanometer semiconductor device manufacturing : which accelerates the development of semiconductor processes and improves yield." Synopsys says that Taurus Process Atomistic offers up to 40-percent faster/more accurate simulation of nanoscale semiconductor device structures. Per the Press Release: "As semiconductor manufacturing scales below the 90-nm node, the tools needed to model and simulate process technology and behavior must consider physics effects that are significantly more complicated than previous generations. Taurus Process Atomistic performs a simulation of the diffusion of atoms within a transistor, which determines the transistor's ability to carry electrical current. In addition to enabling successful process development, the precise simulation of these effects is critical to the ability to characterize transistor power and performance." Don MacMillen, Vice President of Engineering in Synopsys' New Ventures Business Unit, is quoted in the Press Release: "By improving the ability to accurately model advanced processes, we are improving our customers' ability to develop chips that will meet yield and performance expectations. Taurus Process Atomistic offers a unique combination of accuracy, simulation speed and integration. Because the number of atoms in each transistor goes down with feature size, atomistic simulation times decrease with each process generation, offering a speed improvement of orders of magnitude over traditional techniques. Taurus Process Atomistic is used by process technology integration teams to more accurately predict certain characteristics and variations of ultra-shallow junctions that impact transistor performance and leakage." TriCN and Tower Semiconductor announced an agreement under which TriCN will provide its Base I/O library and a suite of high-performance interface IP to Tower for use in their 0.18-micron process. Tower says it will make this IP available to customers designing high-performance chips for production at Tower's Fab 2 facility. Sergio Kusevitzky, Vice President of IP and Design Services with Tower Semiconductor, is quoted in the Press Release: "We're standardizing on TriCN technology for our interface IP needs because of their distinguished track record developing high-performance interfaces. Furthermore, the flexibility of their Base I/O library allows customers with a wide range of design applications to successfully develop chips with minimal risk. We believe this is a key benefit for customers designing next-generation ICs for production in our fab." The X Initiative announced that UMC is the first pure-play foundry to become a member of the semiconductor supply-chain consortium. UMC says it is now ready to accept X Architecture designs for fabrication at the 180-nanometer, 150-nanometer, and 130-nanometer process nodes. Per the Press Release: "The availability of production fabrication for X Architecture designs is a critical step toward broad commercial adoption of this new chip-wiring architecture. The X Architecture represents a new way of orienting a chip's microscopic interconnecting wires using diagonal pathways, as well as the traditional right angle, or 'Manhattan,' configuration. By enabling designs with significantly less wire and fewer vias (the connectors between wiring layers), the X Architecture can provide significant, simultaneous improvements in chip performance, power consumption and cost." I had a chance to speak by phone with Aki Fujimura on December 10th about the announcement and the X Initiative in general. Fujimura is an X Initiative Steering Group Member and CTO for New Business Incubation at Cadence Design Systems, Inc. He told me, "This UMC announcement is important, coming on the heels as it does of the announcement from Toshiba last month that they've released functional silicon with X architecture - a block of a particular, highly confidential 90-nanometer chip. One thing that's important to point out here is that not only is Toshiba announcing the world's first 90-nanometer functional test chip using the X architecture, but they've produced it using their regular flows. Toshiba is ready [for X], and now UMC is the first pure-play foundry to be ready as well. [Clearly], the X Initiative will be producing chips in 2004. The X Initiative consortium published a road map in 2001, which said that 2004 would be the year of production. Now it's clear that it will be." "People often ask us what kind of chips the X architecture is relevant to in comparison with the conventional Manhattan architecture. Our answer is that anyone who cares about the costs of volume, performance, or power consumption on the chip should care about X architecture, because we can show simultaneous improvements in all 3 of these dimensions. In the consumer space, the volume aspect and lower power are important. For the processor people - microprocessors, processor cores, DSPs, network processors, anything that has processor in the name - those are likely to be the kinds of chips that care about performance and speed. Using the X architecture, these people won't have to [restrict improvements] in just one area, they'll get improvements in all of them." "Of course, to the extent that any change in technology is costly, the costs of moving over to the X architecture [from traditional architectures] will have to be justified. But the X architecture has been carefully designed so that it's inherently sideways and backwards compatible with the traditional Manhattan architecture. Data compilers, datapath compilers, existing pieces of IP - these are all completely compatible between Manhattan and X. There's no need to spend any extra energy on new IP at all. Now if you say that you have an ARM core and you're choosing to implement that core in an X architecture, there will of course be some costs there." "Why doesn't everyone move over to the X architecture? Well, this is somewhat of a controversial point. I would say that, eventually, everybody should be doing X, but that eventuality will probably not be here until about 2010. First the high-end, sophisticated customers will adopt the technology, and then it will gradually gain wider acceptance." "Having said this and given that the current world is both Manhattan and X, what's important to remember is that there are advantages to both. Manhattan's architecture, tools, and methodology are the status quo. People are used to it and there's little resistance to using it. But in places where X shows a particular advantage - and X is very strong in random logic - people are going to make the mental switch over [to the new technology]. Say you've got a million gates or more of random logic, then the X architecture is suitable. If you have less than that and the rest of the chip is dominated by analog or memory or custom structure things, then today there's probably not enough justification to overcome the psychological barrier of changing." "Today, the X architecture is enabled by IP uniquely provided by Cadence. If you want to use the X architecture today, you do have to use the Cadence tools. And yes, you're right - if by 2010 there's widespread acceptance, of course Cadence will be in a very strong and unique position at that point. But we have a very open source approach today - there are 39 members who have joined the X initiative consortium so far. Over half of those members are actively engaged in engineering projects to prove that X is viable. And the reason why we've got that level of participation is specifically because we have an open and collaborative approach [to the thing]." "We think of the X Initiative as one of the first collaborative efforts towards true DFM - design-for-manufacturing - initiatives. X has always provided a strong coupling between manufacturing and design, which is why it is one of the great examples of DFM technology. And one of the things that is always worth repeating is that the X architecture is not solely enabled by innovation in routing. Some people thing the technology is about new routing, but it's really about a whole set of improvements including [developments] in clock timing and power. In order to get all of those improvements, it's not sufficient to just [have improvements] in routing. It's important to do placement and extraction as well. The X architecture is making improvements in all of these areas." Newsmakers Beach Solutions has appointed Duncan Nightingale as its European Strategic Accounts Manager. Nightingale will further develop relationships with the company's major accounts and direct the company's new business drive in Europe. Prior to joining Beach, Nightingale worked for various companies including Verisity, Avanti, Analogy, Vantage and LSI Logic. He holds a BSc in Engineering Science and a Masters degree in VLSI Design & Management Studies from Durham University. Mentor Graphics Corp. and the Microprocessor Research and Development Center (MPRC) of Peking University in Beijing, China, announced the opening of the first SoC verification training Center in China. The training facility focuses on training both domestic and overseas engineers to resolve the simulation and verification issues associated with ultra large-scale ASIC designs. Recognizing the essential nature of emulation technology in verifying multimillion gate SoC designs, the center is introducing the Mentor Graphics VStationPRO emulator, a product capable of modeling the performance of the largest ASIC designs in real-time. The center is accredited as the only training site in China to provide regular training on emulation technology. Mentor says that by collaborating with the MPRC on emulation technology, the company continues a long-standing technology relationship with the university. The MPRC has also applied DFT, IC physical verification, FPGA design, and high-speed PCB tools for applications in areas including microprocessor design and verification to hardware and software co-design. Mentor says the VStationPRO is the most advanced ASIC verification technology to be deployed by the center. Professor Cheng Xu, Director of the MPRC and member of the Integrated Circuit Expert Panel of the National High Technology Development Program (863 Program), is quoted: "The new center for SoC Verification builds upon the past success we've had with products from Mentor Graphics. The Mentor Graphics emulation technology greatly bolsters the domestic capabilities for ASIC verification and through the center we will be able to train world-class engineering talent." Nassda Corp. announced that it has been issued a patent - "Transistor Level Circuit Simulator Using Hierarchical Data" (#6,577,992) - by the U.S. Patent and Trademark Office. The company says, "This is the first patent issued to Nassda and relates to the validation of the functionality and performance of microelectronic circuits prior to fabrication. The invention describes how the hierarchical nature of microelectronic circuits may be used to simulate the electrical behavior of very large circuits while minimizing the simulation time and memory required. Consequently, circuit designers can perform full-chip circuit simulations in a reduced amount of time." The company also announced that its CRITIC product was named one of EDN Magazine's Top 100 Products of the Year, in a special report published in the December 11, 2003 issue. TransEDA has appointed Jean-Luc Bouvresse as CEO of the company. Previously, Bouvresse - who has 20+ years' experience in the semiconductor industry - served as Vice President and General Manager of Philips Semiconductors, and most recently as COO and Vice President of Sales at Philips' spin-off, Adelante Technologies. He has also served in executive roles at Intel, Apple, and VLSI. TransEDA says that Bouvresse will be responsible for building a profitable organization by merging the technologies of TransEDA and TNI-Valiosys, which will provide tools for customers needing coverage and verification in SoC design. Marc Frouin, CEO of TNI-Valiosys, the holding company of TransEDA, is quoted in the Press Release: "We are very pleased to welcome Jean-Luc as Chief Executive Officer of TransEDA. Jean-Luc brings the expertise of strong multinational management and business development in the System-on-a-Chip market. He has shown that he can multiply business results several times over, and that he can manage various size organizations from the start-up phase up to over $800 million." Verisity Ltd. announced that Silicon Image has joined Verisity's Pure IP program. The companies say that the program enables Silicon Image to provide its customers with automated processes, technologies and methodologies for integrating Silicon Image's IP cores based on the Serial ATA (SATA), High-Definition Multimedia Interface (HDMI) and Digital Visual Interface (DVI) industry standards. As a member of the program, Silicon Image verifies its cores using Verisity's Verification Process Automation (VPA) "solutions." Silicon Image then packages each core's verification environment into an executable form - a "verification toolkit" - and delivers those toolkits along with the IP to their customers. Also from Verisity - The company announced that Douglas Fairbairn, who joined Verisity's board in September 2003, has been appointed Chairman of the Board. Per the Press Release: "Fairbairn's previous positions include: Founder of VLSI Technology and General Manager of its ASIC Division, Founder and CEO of Redwood Design Automation, General Manager of the Alta Division at Cadence, President of the VSI Alliance SoC industry consortium, and President and CEO of Simutech Corp. Fairbairn was also Founder and Publisher of VLSI Design Magazine. Early in his career, he was a systems engineer at Xerox Palo Alto Research Center. He has BSEE and MSEE degrees from Stanford University." Acquisition - Far more profound, however, is the news on December 11th that Verisity Ltd. and Axis Systems, Inc. have announced a definitive agreement for Verisity to acquire Axis. Axis is a privately held company. The companies say that "the acquisition will enable Verisity to create a comprehensive and highly differentiated VPA (Verification Process Automation) platform to exploit multiple discontinuities in the rapidly changing functional verification market. According to Gartner Dataquest, this market is expected to grow beyond $1 billion in the next few years." Moshe Gavrielov, CEO at Verisity, is quoted in the Press Release: "This significant acquisition will expand our breadth of offerings and greatly expand our market. Axis brings unique world-class technology, and together we will create the only company that is capable of providing a total VPA platform that will take projects from specification to verification closure. Customers need solutions that deliver process productivity, predictability and quality of results. This requires significantly more than just engines and languages. The VPA Platform, combining Verisity and Axis' technology, is the compelling answer to these requirements." Mike Tsai, President and CEO at Axis Systems, is also quoted: "We are excited to join forces with Verisity for their technology and clear leadership in verification. This is clearly a market discontinuity we are addressing, driven by hardware-software SoC designs that require a new level of intelligence via process automation, and a new level of easily accessible and scalable verification performance. The combination of Verisity and Axis' technology will create the only company capable of meeting the growing verification challenges of nanometer designs." Mike Tsai will become executive vice president and general manager of the platform division reporting directly to Moshe Gavrielov. Axis Systems' audited revenue for the fiscal year that ended July 31, 2003 exceeded $20 million and the company currently employs about 90 people worldwide. Verisity will acquire Axis for approximately $80 million in cash and stock, with the stock portion representing less than 20 percent of Verisity's outstanding shares. The transaction is expected to close in Q1 2004. Bits & Sound Bytes 1 - The Single Electron Transistor Texas Instruments Inc. and the Swiss Federal Institute of Technology of Lausanne are describing a potential way to use single electron transistors (SETs) to perform logic functions and reduce the size and power consumption of future semiconductor devices. A paper presented at IEDM (Washington, D.C.) shows that a combination of SETs and standard CMOS transistors can provide enough gain and current drive to perform logic functions at a much smaller scale than will eventually be possible with CMOS alone. Per the Press Release: "SETs can potentially take the industry all the way to the theoretical limit of electrons for computing applications by allowing the use of a single electron to represent a logic state. There is general agreement in the semiconductor industry that standard silicon CMOS should support scaling for the next ten to fifteen years using traditional Field Effect Transistors (FETs) that use large numbers of electrons in operation. Advancement beyond that will require vastly different approaches in materials and architecture to cost effectively manage the signal integrity and heat problems created by so many tightly packed transistors. A range of alternative state devices have shown promise, but the light, fast and strongly interacting 'charged electron' provided the foundation of modern computing. The next challenge for researchers is to manufacture reliably many SETs in a CMOS compatible process on silicon. The first application for SETs could be for memory and special applications in metrology, such as primary thermometers and super sensitive electrometers." Christoph Wasshuber, a TI scientist and co-author of the IEDM paper, is also quoted in the Press Release: "Looking out ten years and beyond, TI sees that the CMOS roadmap will need help to continue to deliver the predictable returns the industry has counted on for decades from Moore's Law. It is starting to look viable for CMOS to continue to play a major role by providing a traditional system interface to millions of radically smaller, lower power, single electron transistors." 2 - Observations on SystemVerilog Cliff Cummings, President of Sunburst Designs, Inc., presented a lengthy tutorial last week at an Accellera Symposium and pinpointed several features in SystemVerilog, which in a perfect world would have been found in Verilog 2001, as well. Cummings said, "We rejected several things in Verilog 2001 because we couldn't reach agreement soon enough to meet our deadline, but they are in SystemVerilog because we did reach agreement and they are important." Some of those features include an auto-increment in the For loop, an enumerated data type, and a record data type. Cummings also told his audience, "For large, top-level ASIC designs, I fully anticipate a 70-percent decrease in the code needed to execute a design. You're going to find that SystemVerilog is definitely less verbose than Verilog!" 3 - Observation on SystemC This from John Cooley the ESNUG guy: "SystemC will be the dominant language when pigs fly!" ( www.esnug.com ) Although from many reports I hear from this corner or that, pigs may yet fly - only time will tell - I take my hat off to someone who's willing to take a stand for his constituency. 4 - The University of Washington I had a marvelous visit to the University of Washington a number of weeks ago. Not only was I enamored of the campus, but I spent 2 fascinating hours discussing a huge range of topics with Professor Carl Sechen, an articulate technologist in the Department of Electrical Engineering. I finished an article based on that conversation several days ago and was in the midst of verifying the technical details via e-mail with Dr. Sechen, when situational irony came a'knocking. I got word that the authorities on campus - in their infinite wisdom - fired my beloved 20-year-old, a junior at UW, from her job as an RA in one of their mega-dorms. Now, you know and I know that into every life a little rain must fall - and my daughter has to learn to take her hard knocks along with the rest of the brotherhood of man - but why a University/employer waits until the afternoon before finals begin to fire an employee/student, and why that termination has to take place in a glass-walled office in full view of an employee's co-workers outside, is beyond comprehension. Not surprisingly, I have concluded that UW is not a place I want to celebrate in print right now. I do celebrate my daughter, however, as a noble and ethical individual. She made a difficult decision in a complex situation, and for that she has lost her job and her home. I'm proud of her and I hope she reads this someday. I hope that she continues to listen to her inner voice about what is right - even when it means making the tougher, less convenient, or less conventional choice. I also sincerely apologize to Dr. Sechen for having taken up his time for nothing. I hope he will allow me to re-visit the article at a later date. In the category of ... Letters to the Editor December 7th - A Day in the Life Letter No. 1 Hi Peggy, I read your article in the latest EDA Weekly with the subject "A Day in the Life, Heaven hath no fury like an editor on deadline." It forced me to think about the career once again. By the way, the luncheon was from which Big One? And who was the host? Thanks and regards, Anon in Engineering (Editor's Note: The name of the company and hosts were intentionally withheld.) Letter No. 2 Peggy, Engineers should think twice before banking on a transition to management to salvage their careers. Though Sales and Marketing are often laid off first, managers frequently are the next to go - sometimes even before the engineers. Sincerely, Anon in Engineering Letter No. 3 Peggy, Your article was a real downer. I have 30 years' experience in engineering and have been laid off 4 times in the past 2 and 1/2 years. I am presently working as a contractor. I have two small children and another on the way and am the sole supporter of the family. I know several people in the same boat that I am - good school, good grades, engineer for 20+ years, with a family, out of a job, and seemingly no prospects. The good thing about my situation is that I have been able to find work continuously for 30 years. I am thinking of getting a P.E. and going into construction, so I can build houses for all the people who are getting rich by firing good engineers and shipping the jobs to India. The problem is that this solution will not be permanent. The innovation and imagination are not in the Indian sub-continent. The semiconductor industry is shooting itself in the foot continuously by ignoring the talent that is in the older engineers. Recently, there was an article in the San Jose Mercury News about older engineers and the fact that the VCs are turning back to them for help in breeding success. What do you think the VCs are really up to? Sincerely, Anon in Engineering Letter No. 4 - A VC responds to Letter No. 3 Peggy, Early-stage venture investors, like Foundation Capital, are drawn to projects that involve smart entrepreneurs, deep technology, and the basis for a good business model. We are really not affected in any way by age of the early team. The advantage that more mature start-up team members have is the value of having worked in an earlier era (pre-Netscape, at least), because many of the characteristics of great teams that resulted in great investments are crucial again. For example - entrepreneurs who want to change the world with their technology; who value building a company with a minimum of cash, and who know that happy/referenceable customers are the most important measure of a successful business. Regards, Mike Schuh Partner, Foundation Capital Letter No. 5 Peggy, I can see that you are very tuned into the problems facing many senior engineers (and I know many personally) who have lost their jobs due to "market" conditions : and that [while] older engineers are looking for work, even the ones that are working cannot be completely secure. Not everyone over the age of 35 becomes obsolete, [however]. While it is true that many engineers fail to keep up with "market" conditions, this is not true of everyone. I know that it is up to me to resolve the "market" conditions if I want to remain in EDA. And I have faith that good things are always around the corner. It is only a matter of locating the corner. Thank you and take care, Ed Caldwell PCB Designer & Librarian Letter No. 6 Peggy, I'm not sure what to make of your editorial regarding the "meeting" in which editors sat around and discussed engineers. The outlook is obviously quite gloomy. Your comment, something like "gloom of dusk turning to dark of night" is apropos, but I kept looking for some real insight to the problem. The truth is that U.S. manufacturing is losing on many fronts, but it's because we've lost the will and the way to innovate. I discovered one thing about U.S. fabs - they're not sure which direction to take on most any kind of innovative manufacturing technology. They seem to want it all "handed" to them. If it requires any real R&D, even the least little bit, a negative inertia takes over and they just can't move. If it isn't plug-and-play, handed to them by a supplier, they're not going to entertain anything new. I'm always amazed that in discussing a new technology with a prospective client, the inevitable question is "Who else is using it?" - it's as if, unless some other company has gone before them, they won't be the leader. Several companies outside the U.S. have adopted new technologies, but in the US we're blind to them. And besides, even with the adoption of innovative technology - for example many European manufacturing technologies - what makes U.S. fabs think that Europeans are just going to open their doors and tell the world everything about what they do? Europe does more in their manufacturing practices than just getting government subsidies - it's no wonder that Airbus is overtaking Boeing. While of course, U.S. aerospace companies get government subsidies, too, if the truth be known. Perhaps someone can argue against the aerospace example - I certainly don't want to oversimplify an obviously complex issue - but as a manufacturing nation, we've got a lot of problems on our hands and a lot of available solutions are going unused. For example - since early 2000, I've worked with a relatively simple, but highly innovative electroplating technology. I got started in this endeavor through the bare board pwb [printed wiring boards] manufacturing industry and discovered that there's a nagging plating problem that just seems to get worse as interconnects get more dense and complex. The problem is electroplating thickness uniformity, or should I say non-uniformity. The problem is inherent in electroplating, not just in electronics manufacturing. My solution to the problem has come to be known as Smart Cathode Shielding. Smart Cathode Shields are driven by available CAD data to compensate for uneven primary and secondary current distribution on the cathode, be it a pwb, a wafer, or an ordinary plumbing fixture. Acceptance by U.S. industry? Paltry! But the acceptance problem isn't specific to just this one industry segment. It's one of the characteristics found in almost all U.S. manufacturing industries. In short, we don't do R&D and we just don't innovate anymore. We've lost the will and the way. Since manufacturers are leaving in droves, it's been my belief that U.S. technological superiority will be one of the only things we have left to sell to the rest of the world and yet U.S. industry is sort of ho-hum. And there's no question that the corporate mentality has drained the profit needed to stay ahead. There's definitely something missing and we've got to change the present course. Let it be said : we didn't build the strength of this country on the current obsession with professional sports, personal comfort, and the excesses of the entertainment industry. Sincerely, Roger Mouton EIMC - Advanced Plating Technologies Letter No. 7 Hi Peggy, I enjoyed the article about the luncheon. Interesting insight. Here are a couple of things/reasons I've seen that have caused [some companies] to struggle recently. Obviously, the budgets aren't there - especially for new shifts in methodology and, as you mentioned in the article, there are fewer engineers on the development teams to do what has to be done. [Meanwhile], it's a really bad time for engineers to raise their hand above the cubicle and say, "Hey, let's try this new stuff!" They are keeping their heads down to get their projects completed and to keep their jobs. It's also true that some companies have ramped up their Design Services team to go out and help customers via the "back door," so to speak. They are getting design wins by using their own tools to "share in the burden" of their customers' design work. The Design Services teams are proving the methodology to "help out the customer," which guarantees the sale of seats afterwards. Regards, Walter McRae Letter No. 8 Hi Peggy, Excellent editorial in the last issue! Glad another editor feels the same way. I've been venting my frustrations - and asking for reader comments - in one of my regular e-columns. Have actually received quite a few responses from engineers on topics like outsourcing, corporate brain-drain, bounties on hackers (the only ones finding the many, many software bugs), etc. Most older engineers that I chat with say they will actively work to prevent their kids from pursuing an engineering career. This trend, plus all the others, are very depressing. Few outside of the press and engineering profession understand the true magnitude - or consequences - of the death of technology innovation in the U.S. Hope you're feeling less "grumpy" in this season of hope. Regards, John Blyler Senior Technology Editor - Wireless Systems Design Magazine Executive Editor, Wireless Systems Design UPDATE e-Newsletter Affiliate Professor, System Engineering, Portland State University Letter No. 9 Hi Peggy, Your column this week on the semiconductor industry is a classic that you should run every year, just like Charles Dickens' "A Christmas Carol". I started out laughing at your commentary about nice, nicer, and nicest. By the time I finished your email, I was so depressed that I left the PC and gobbled down an entire slice of leftover pizza which I had been saving for dinner. I have several comments on your editorial, and not necessarily in this order: I promise never to do an event on Thursday. Social events with press don't work well - sometimes. I agree with you that the adversarial nature of a relationship must be maintained, but only to a degree!! While I understand your comment, I believe that the relationship between the industry press and PR folks should be strong because PR people have a dedicated interest in sustaining the vitality of the industry press. PR people understand the role of the industry media far better than any other constituency you have, but as a group we have been unable to exercise assistance. In part this is because ad agencies, media reps and publishing companies see our roles as separate from their business interface. Your comments on engineers are dead-on correct, as are the comments on what's happened to companies who have displaced their senior engineers. I would take your commentary further to say that the health and wealth and global standing of the U.S. electronics industry, and the U.S. in turn, is at stake. We are in an intellectual property battle that we are losing, in my view, due to our inability to design new business models that protect our ability to be competitive and build revenue. As for the comments on ARM, this is a problem in our industry. It is easy to assume that a problem belongs to another company, when it really belongs to the entire industry. Replies from your hosts re: FPGAs, structured ASICs (new term for old term...ASIC) are wrong. One need only look at Xilinx to figure out how lucrative FPGAs CAN be. The PR folks are ingenuous (not 'ingenious') if they think they can invite industry press to an event and avoid tough questions. I'm glad these questions were asked. The gift. In this regard, I fear you...and I...and everyone else...have become jaded. A gift used to be just that, a gift. An expression of gratitude and friendship. Now they are viewed with distrust and even rejected. I gave a colleague a book last year - one that I had read, enjoyed, learned from and felt so valuable that I wanted others to read it. I even published a review on it. Yet, one person replied with a scathing email asking if I thought he wasn't smart enough to figure all 'this stuff' out. I was crushed. Look at the gift as simply a gift. You should not read more in to it, or you will become its captive. All the best, Barbara Kalkis Maestro Public Relations November 17th - Peace & Prosperity Letter No. 10 Peggy, "Jobless recovery," 8.7 million unemployed, ... While it may be difficult to keep things in perspective when you are one of the 8.7 million unemployed, perhaps [your readers] may be too young to recall the stagflationary times of the late 1970's. The unemployment rate in Trumbull County, Ohio, (my place of birth) was 15 percent or higher. Okay, Trumbull County is no hot bed of high-tech (or any industry other than GM/Delphi these days), but it wasn't that long ago (in mid-to-late 1990's) that economists believed that a 6 percent national unemployment rate was the BEST we could expect. Sure, the last 3 years have been brutal for high tech. But, 6-point-something-percent unemployment counts as a very mild recession by historical standards. Again, it is hard to stay upbeat when you are currently downtrodden. However, if you happen to find yourself "liberated to explore new career opportunities," then do so. High unemployment in Trumbull County led to my own personal odyssey of eventually getting a BS and an MS in Computer Science - achievements made possible when I left Trumbull County and my comfort zone in search of greener pastures. I have been fortunate to graze in the high-tech pastures for the past 18 years. However, if I should become one of the downtrodden, then I will search again for greener pastures, wherever they may lie. Regards, Stephen Bailey --Peggy Aycinena is a Contributing Editor and can be reached by clicking here . You are registered as: [dolinsky@gsu.by]. CafeNews is a service for EDA professionals. EDACafe respects your online time and Internet privacy. To change your newsletter's details, including format and frequency, or to discontinue this service, please navigate to . If you have questions about EDACafe services, please send email to edaadmin@ibsystems.com . Copyright c 2003, Internet Business Systems, Inc. - 11208 Shelter Cove, Smithfield, VA 23420 - 888-44-WEB-44 - All rights reserved.